Multi-input amplifier with degeneration switching without the use of switches

ABSTRACT

Disclosed herein are signal amplifiers that include a plurality of switchable amplifier architectures so that particular gain modes can use dedicated amplifier architectures to provide desired characteristics for those gain modes, such as low noise figure or high linearity. The disclosed signal amplifier architectures provide tailored impedances using a degeneration block or matrix without using switches in the degeneration switching block. The disclosed signal amplifier architectures provide a plurality of gain modes where different gain modes use different paths through the amplifier architecture. Switches that are used to select the path through the amplifier architecture also provide targeted impedances in a degeneration block or matrix. The switches that select the gain path are provided in the amplifier architecture and are thus not needed or used in the degeneration block, thereby reducing the size of the package for the amplifier architecture.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. Prov. App. No. 63/132,926 filed Dec. 31, 2020 and entitled “MULTI-INPUT AMPLIFIER WITH DEGENERATION SWITCHING WITHOUT THE USE OF SWITCHES,” which is expressly incorporated by reference herein in its entirety for all purposes.

BACKGROUND Field

The present disclosure generally relates to amplifiers for wireless communication applications.

Description of Related Art

Wireless communication devices typically include components in a front-end module that are configured to amplify received radio-frequency (RF) signals. The front-end module can include a plurality of gain modes to provide different levels of amplification.

SUMMARY

According to a number of implementations, the present disclosure relates to a variable-gain signal amplifier configured to provide a plurality of gain modes. The amplifier includes an input node configured to receive an input signal. The amplifier includes an output node configured to provide an amplified output signal. The amplifier includes a first active core configured to receive the input signal and to generate the amplified output signal for the output node. The amplifier includes a second active core configured to receive the input signal and to generate the amplified output signal for the output node. The amplifier includes a gain mode selector configured to direct the input signal to the first active core in a first gain mode and to direct the input signal to the second active core in a second gain mode different from the first gain mode. The amplifier includes a degeneration matrix configured to provide tailored inductances depending on a signal path determined by the gain mode selector, the degeneration matrix not including any switches.

In some embodiments, the input signal comprises a radio frequency signal. In some embodiments, the amplifier further includes a switchable reference bias circuit configured to provide a first reference bias current to the first active core in the first gain mode and a second reference bias current to the second active core in the second gain mode. In some embodiments, the gain mode selector is configured to selectively provide a bypass path that bypasses the first active core and the second active core and an amplification path that passes through either the first active core or the second active core. In some embodiments, the degeneration matrix is configured to provide a first inductance to the first active core and a second inductance different from the first inductance to the second active core. In some embodiments, the tailored impedances are configured to provide improved linearity in the amplified output signal relative to a variable gain stage that is not coupled to the degeneration matrix with the tailored impedances.

In some embodiments, the degeneration switching block is configured to provide a first tailored impedance for the first gain mode and a second tailored impedance for the second gain mode. In further embodiments, the first tailored impedance is greater than the second tailored impedance and the first gain level is less than the second gain level.

In some embodiments, the first active core is configured to have a lower noise figure than the second active core. In further embodiments, the second active core is configured to have a higher linearity than the first active core. In further embodiments, the first gain mode is higher than the second gain mode.

In some embodiments, the amplifier further includes a plurality of input nodes. In further embodiments, the amplifier is configured to receive a plurality of input signals at the plurality of input nodes, individual received signals having frequencies within different signal frequency bands. In further embodiments, the amplifier is configured to amplify signals received at individual input ports independent of amplification of other received signals.

In some embodiments, the amplifier further includes a bypass block coupled to the input node and configured to be activated in a low gain mode to provide a bypass path that does not include the first active core and the second active core. In some embodiments, each of the first active core and the second active core include a cascode buffer coupled to an output of a gain stage.

According to a number of implementations, the present disclosure relates to a front-end module that includes a packaging substrate. The module also includes a variable gain signal amplifier implemented on the packaging substrate, the variable gain signal amplifier including a first active core configured to receive an input signal and to generate an amplified output signal, a second active core configured to receive the input signal and to generate the amplified output signal, a gain mode selector configured to direct the input signal to the first active core in a first gain mode and to direct the input signal to the second active core in a second gain mode, a degeneration matrix configured to provide tailored inductances depending on a signal path determined by the gain mode selector, the degeneration matrix not including any switches, and a controller implemented to control the variable gain signal amplifier to provide a plurality of gain modes including the first gain mode and the second gain mode.

In some embodiments, the gain signal amplifier further includes a switchable reference bias circuit configured to provide independent bias currents to the first active core and to the second active core. In some embodiments, the first active core is configured to have a lower noise figure than the second active core and the second active core is configured to have a higher linearity than the first active core.

According to a number of implementations, the present disclosure relates to a wireless device. The wireless device includes an antenna. The wireless device includes a filter assembly coupled to the antenna to receive signals and to direct frequency bands along select paths. The wireless device includes a variable gain signal amplifier including a first active core configured to receive an input signal and to generate an amplified output signal, a second active core configured to receive the input signal and to generate the amplified output signal, a gain mode selector configured to direct the input signal to the first active core in a first gain mode and to direct the input signal to the second active core in a second gain mode, and a degeneration matrix configured to provide tailored inductances depending on a signal path determined by the gain mode selector, the degeneration matrix not including any switches. The wireless device includes a controller implemented to control the variable gain signal amplifier to provide a plurality of gain modes.

For purposes of summarizing the disclosure, certain aspects, advantages and novel features have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment. Thus, the disclosed embodiments may be carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example wireless device having a primary antenna and a diversity antenna.

FIG. 2 illustrates an example diversity receiver (DRx) configuration including a DRx front-end module (FEM).

FIG. 3A illustrates an example variable gain amplifier configuration that includes a switchable reference bias, a gain mode selector, a bypass block, and a plurality of amplifier architectures configured to receive input signals and to selectively amplify the received signals with a selected amplifier architecture or to provide a bypass path through the bypass block.

FIG. 3B illustrates another example variable gain amplifier configuration that includes the same components as the variable gain amplifier configuration of FIG. 3A, with additional components.

FIG. 4 illustrates an amplifier that includes an input stage with individual input paths.

FIG. 5 illustrates a variable-gain signal amplifier that includes a plurality of active cores in a variable-gain stage configured to receive an input signal and to generate an amplified output signal.

FIGS. 6A and 6B illustrate an example variable gain amplifier configuration that is configured similarly to the variable gain amplifier of FIG. 3B.

FIG. 7 illustrates another example amplifier configuration which is similar to the amplifier configuration of FIGS. 6A and 6B.

FIGS. 8A-8F illustrate examples of operating modes of the variable gain signal amplifier configuration of FIG. 6A.

FIG. 9 illustrates that some or all of the amplifier configurations having the combinations of features described herein, can be implemented, wholly or partially, in a module.

FIG. 10 depicts an example wireless device having one or more advantageous features described herein.

DETAILED DESCRIPTION OF SOME EMBODIMENTS

The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.

Overview

Signal amplifiers in wireless devices, such as low noise amplifiers (LNAs) and power amplifiers (PAs), can be designed to amplify signals while providing desired characteristics, such as a targeted noise figure (NF) or targeted linearity. Certain wireless devices are designed to provide a plurality of gain modes, providing different levels of amplification. However, in such devices, the signal amplifiers may suffer from reduced performance in one or more of the gain modes and thus may fail to achieve the desired characteristics across the plurality of gain modes. For example, linearity may suffer across the plurality of gain modes.

Accordingly, disclosed herein are signal amplifiers that include a plurality of switchable amplifier architectures so that particular gain modes can use dedicated amplifier architectures to provide desired characteristics for those gain modes, such as low noise figure or high linearity. The disclosed signal amplifier architectures provide tailored impedances using a degeneration block or matrix without using switches in the degeneration switching block. The disclosed signal amplifier architectures provide a plurality of gain modes where different gain modes use different paths through the amplifier architecture. Switches that are used to select the path through the amplifier architecture also provide targeted impedances in a degeneration block or matrix. The switches that select the gain path are provided in the amplifier architecture and are thus not needed or used in the degeneration block, thereby reducing the size of the package for the amplifier architecture, improving the noise figure (NF), improving impedance matching, and eliminating the need for control logic associated with the degeneration block or matrix.

Rather than providing a single amplifier core or architecture for all gain modes, the disclosed signal amplifiers provide a plurality of amplifier cores allowing individual amplifier cores to be designed for particular gain modes to achieve desired characteristics or to enhance particular advantages while reducing other disadvantages. For example, an amplifier architecture for high gain modes can be designed with a focus on achieving a targeted noise figure. As another example, an amplifier architecture for low gain modes can be designed with a focus on achieving a targeted linearity. The signal amplifier can then switch between using the high gain mode amplifier core (or the low NF core) for high gain modes, and the low gain amplifier core (or the high linearity core) for low gain modes. The amplifier architectures include a degeneration block or matrix to further improve signal linearity. In some embodiments, the degeneration block or matrix is implemented as part of a particular amplifier core. In such embodiments, signals from any amplifier core can be directed to the degeneration block or matrix that is part of the particular amplifier core. The degeneration block or matrix is implemented without using switching or switches in the degeneration block or matrix.

One advantage of the disclosed amplifiers with switchable amplifier cores is that such a configuration allows for gain modes to be selectively directed to targeted amplifier architectures to achieve desired characteristics. This may change during operation of the wireless device so that, while operating in a particular gain mode, signals can be directed to a first active core during a first time period to achieve a particular set of advantages, and while operating in the same gain mode signals can be directed to a second active core during a second time period to achieve a different (possibly overlapping) set of advantages.

In some embodiments, the amplifiers disclosed herein can also be configured to receive multiple inputs and route the signals to appropriate amplifier architectures. In some embodiments, the signal amplifiers disclosed herein can perform multi-input processing without using a switch between inputs. In some embodiments, the amplifiers disclosed herein can be configured to achieve a desired or targeted bias current matching by using a switchable reference bias core. In some embodiments, the signal amplifiers disclosed herein can improve gain mode performance through the use of individual input matching per active core.

FIG. 1 illustrates an example wireless device 100 having a primary antenna 160 and a diversity antenna 170. The wireless device 100 includes an RF module 106 and a transceiver 104 that may be controlled by a controller 102. The transceiver 104 is configured to convert between analog signals (e.g., radio-frequency (RF) signals) and digital data signals. To that end, the transceiver 104 may include a digital-to-analog converter, an analog-to-digital converter, a local oscillator for modulating or demodulating a baseband analog signal to or from a carrier frequency, a baseband processor that converts between digital samples and data bits (e.g., voice or other types of data), or other components.

The RF module 106 is coupled between the primary antenna 160 and the transceiver 104. Because the RF module 106 may be physically close to the primary antenna 160 to reduce attenuation due to cable loss, the RF module 106 may be referred to as a front-end module (FEM). The RF module 106 may perform processing on an analog signal received from the primary antenna 160 for the transceiver 104 or received from the transceiver 104 for transmission via the primary antenna 160. To that end, the RF module 106 may include filters, power amplifiers, low noise amplifiers, band select switches, attenuators, matching circuits, and other components.

When a signal is transmitted to the wireless device 100, the signal may be received at both the primary antenna 160 and the diversity antenna 170. The primary antenna 160 and diversity antenna 170 may be physically spaced apart such that the signal at the primary antenna 160 and diversity antenna 170 is received with different characteristics. For example, in one embodiment, the primary antenna 160 and the diversity antenna 170 may receive the signal with different attenuation, noise, frequency response, and/or phase shift. The transceiver 104 may use both of the signals with different characteristics to determine data bits corresponding to the signal. In some implementations, the transceiver 104 selects from between the primary antenna 160 and the diversity antenna 170 based on the characteristics, such as selecting the antenna with the highest signal-to-noise ratio. In some implementations, the transceiver 104 combines the signals from the primary antenna 160 and the diversity antenna 170 to increase the signal-to-noise ratio of the combined signal. In some implementations, the transceiver 104 processes the signals to perform multiple-input/multiple-output (MiMo) communication.

In some embodiments, the diversity antenna 170 is configured to receive signals within multiple cellular frequency bands and/or wireless local area network (WLAN) frequency bands. In such embodiments, the wireless device 100 can include a multiplexer, switching network, and/or filter assembly coupled to the diversity antenna 170 that is configured to separate the diversity signal into different frequency ranges. For example, the multiplexer can be configured to include a low pass filter that passes a frequency range that includes low band cellular frequencies, a bandpass filter that passes a frequency range that includes low band WLAN signals and mid-band and high-band cellular signals, and a high pass filter that passes a frequency range that includes high-band WLAN signals. This example is merely for illustrative purpose. As another example, the multiplexer can have a variety of different configurations such as a diplexer that provides the functionality of a high pass filter and a low pass filter.

Because the diversity antenna 170 is physically spaced apart from the primary antenna 160, the diversity antenna 170 can be coupled to the transceiver 104 by a transmission line, such as a cable or a printed circuit board (PCB) trace. In some implementations, the transmission line is lossy and attenuates the signal received at the diversity antenna 170 before it reaches the transceiver 104. Thus, in some implementations, gain is applied to the signal received at the diversity antenna 170. The gain (and other analog processing, such as filtering) may be applied by the diversity receiver module 108. Because such a diversity receiver module 108 may be located physically close to the diversity antenna 170, it may be referred to as a diversity receiver front-end module, examples of which are described in greater detail herein.

The RF module 106 and the diversity receiver module 108 include respective variable gain amplifiers 110 a, 110 b configured to provide a plurality of gain modes to amplify signals from the primary antenna 160 and the diversity antenna 170, respectively. The variable gain amplifiers 110 a, 110 b can include a plurality of amplifier architectures 120 and a degeneration matrix 130 that changes inductance based at least in part on a gain mode of the variable gain amplifier 110 a, 110 b. Individual amplifier architectures 120 can be activated by the variable gain amplifier 110 a, 110 b based at least in part on an operating gain mode. The activated amplifier architecture can be designed to provide targeted or desired characteristics for the particular gain mode(s) directed to the architecture. In this way, desired characteristics can be enhanced for individual gain modes. Signals received at the variable gain amplifiers 110 a, 110 b can be amplified using a particular amplifier architecture selected by the variable gain amplifier 110 a, 110 b, or the signals can be allowed to bypass the amplifier architectures 120, as described in greater detail herein. The selected amplifier architecture 120, the inductance of the degeneration matrix 130, the bypass path, and/or the gain mode of the variable gain amplifier 110 a, 110 b can be controlled by the controller 102. The degeneration matrix 130 can be configured to provide an inductance that increases performance of the variable gain amplifier 110 a, 110 b relative to an amplifier with fixed inductance. Performance can be increased by increasing linearity and/or by reducing noise introduced during amplification, for example. The variable gain amplifier 110 a, 110 b can receive multiple input signals and output a single signal or a plurality of output signals. The degeneration matrix 130 can be configured to not include any switches. The inductance provided by the degeneration matrix 130 can be controlled by way of switches that select a gain stage path (e.g., in the amplifier architectures 120 or in a gain stage) in the variable gain amplifier 110 a, 110 b.

Advantageously, by removing switches from the degeneration matrix 130, area on the die that includes the amplifier 110 a, 110 b can be reduced or the area that otherwise would have included switches can be repurposed. Furthermore, removing switches from the degeneration matrix 130 improves the noise figure (NF) due at least in part to the reduction of losses associated with additional series switches in the amplifier path. Additionally, increasing the input impedance makes matching the previous stage easier, reducing impedance mismatch performance losses. In addition, the degeneration matrix 130 that does not include switches can advantageously provide tailored impedances without requiring associated control logic to control switches in the degeneration matrix 130.

The variable gain amplifier 110 a, 110 b can advantageously achieve targeted or improved linearity by using a dedicated amplifier architecture with tailored electrical properties. Similarly, the variable gain amplifier 110 a, 110 b can advantageously achieve targeted or improved NF by using a dedicated amplifier architecture with tailored electrical properties. Likewise, the variable gain amplifier 110 a, 110 b can advantageously achieve targeted or improved NF and/or linearity using a degeneration matrix 130 with tailored inductances. The degeneration matrix 130 can advantageously provide these tailored inductances without using switches in the degeneration matrix 130. The variable gain amplifier 110 a, 110 b can provide targeted or improved input to output isolation through the use of a shunt switch in a bypass path and/or in one or more of the amplifier architectures 120.

The controller 102 can be configured to generate and/or send control signals to other components of the wireless device 100. In some embodiments, the controller 102 provides signals based at least in part on specifications provided by the mobile industry processer interface alliance (MIPI® Alliance). The controller 102 can be configured to receive signals from other components of the wireless device 100 to process to determine control signals to send to other components. In some embodiments, the controller 102 can be configured to analyze signals or data to determine control signals to send to other components of the wireless device 100. The controller 102 can be configured to generate control signals based on gain modes provided by the wireless device 100. For example, the controller 102 can send control signals to the variable gain amplifiers 110 a, 110 b to control the gain mode. Similarly, the controller 102 can be configured to generate control signals to select amplifier architectures 120 to activate for particular gain modes. The controller 102 can be configured to generate control signals to control the variable gain amplifier 110 a, 110 b to provide a bypass path. The controller 102 can be configured to select a gain path through the variable gain amplifier 110 a, 110 b that thereby controls the inductances or impedances provided by the degeneration matrix 130, as described herein.

In some implementations, the controller 102 generates amplifier control signal(s) based on a quality of service metric of an input signal received at the input. In some implementations, the controller 102 generates the amplifier control signal(s) based on a signal received from a communications controller, which may, in turn, be based on a quality of service (QoS) metric of the received signal. The QoS metric of the received signal may be based, at least in part, on the diversity signal received on the diversity antenna 170 (e.g., an input signal received at the input). The QoS metric of the received signal may be further based on a signal received on a primary antenna 160. In some implementations, the controller 102 generates the amplifier control signal(s) based on a QoS metric of the diversity signal without receiving a signal from the communications controller. In some implementations, the QoS metric includes a signal strength. As another example, the QoS metric may include a bit error rate, a data throughput, a transmission delay, or any other QoS metric. In some implementations, the controller 102 controls the gain (and/or current) of the amplifiers in the variable gain amplifiers 110 a, 110 b. In some implementations, the controller 102 controls the gain of other components of the wireless device 100 based at least in part on an amplifier control signal.

The variable gain amplifiers 110 a, 110 b may include a step-variable gain amplifier configured to amplify received signals with a gain of one of a plurality of configured amounts indicated by an amplifier control signal. In some implementations, the variable gain amplifiers 110 a, 110 b may include a continuously-variable gain amplifier configured to amplify received signals with a gain proportional to or dictated by the amplifier control signal. In some implementations, the variable gain amplifiers 110 a, 110 b may include a step-variable current amplifier configured to amplify received signals by drawing a current of one of plurality of configured amounts indicated by the amplifier control signal. In some implementations, the variable gain amplifiers 110 a, 110 b may include a continuously-variable current amplifier configured to amplify received signals by drawing a current proportional to the amplifier control signal.

FIG. 2 illustrates an example diversity receiver (DRx) configuration 200 including a DRx front-end module (FEM) 208. It is to be understood that the features of the DRx FEM 208 can be implemented in any front-end module described herein, such as the RF module 106 described herein with reference to FIG. 1. The DRx configuration 200 includes a diversity antenna 170 that is configured to receive a diversity signal and to provide the diversity signal to the DRx FEM 208 through a filter assembly 272. The filter assembly 272 can include a multiplexer, for example, that is configured to selectively direct signals within targeted frequency ranges along respective paths to an amplifier 210 having a multi-input stage 212 that is coupled to amplifier architectures 220 that include a low NF core 222 and a high linearity core 224. The signals can be radio frequency (RF) signals that include, for example and without limitation, cellular signals (e.g., low-, mid-, high- and/or ultra-high-band cellular frequencies), WLAN signals, BLUETOOTH® signals, GPS signals, and the like.

The multi-input gain stage 212 is coupled to a degeneration matrix 230 that does not include switches. The degeneration matrix 230 is configured to provide tailored impedances for individual paths through the multi-input gain stage 212. In some embodiments, a gain mode of the amplifier 210 determines the path through the multi-input gain stage 212 which in turn determines the impedance or inductance provided by the degeneration matrix 230. Similarly, the gain mode of the amplifier 210 determines which core 222, 224 of the amplifier architectures 220 is used in amplifying the diversity signal.

The DRx FEM 208 is configured to perform processing on the diversity signals received from the filter assembly 272. For example, the DRx FEM 208 may be configured to filter the diversity signals to one or more active frequency bands that can include cellular and/or WLAN frequency bands. The controller 102 can be configured to control the DRx FEM 208 to selectively direct signals to targeted filters to accomplish the filtering. As another example, the DRx FEM 208 may be configured to amplify one or more of the filtered signals using a particular active core 222, 224 of the amplifier architectures 220. To that end, the DRx FEM 208 may include filters, low-noise amplifiers, band select switches, matching circuits, and other components. The controller 102 can be configured to interact with components in the DRx FEM 208 to intelligently select paths for the signals through the DRx FEM 208. As a consequence of the path selected by the controller 102, the degeneration matrix 230 provides an inductance corresponding to the selected path without the use of switches in the degeneration matrix 230 itself. As a result, the controller 102 advantageously does not include control logic to control switches within the degeneration matrix 230 thereby simplifying the controller 102.

The DRx FEM 208 transmits at least a portion of the processed diversity signals to the transceiver 104. The transceiver 104 may be controlled by the controller 102. In some implementations, the controller 102 may be implemented within the transceiver 104.

The DRx FEM 208 can be configured to provide a plurality of gain modes. For the plurality of gain modes, different amplifier architectures 220 can be selected to amplify input signals. In one or more gain modes, the signals can be routed to a low NF core 222 to amplify signals with an emphasis on achieving a low NF. In some embodiments, signals are routed to the low NF core 222 in high gain modes. In one or more gain modes, the signals can be routed to a high linearity core 224 to amplify signals with an emphasis on achieving a targeted linearity. In some embodiments, signals are routed to the high linearity core 224 in low or medium gain modes. It is to be understood that different amplifier architectures may also be implemented that provide targeted performance characteristics including, for example and without limitation, NF, linearity, gain, bandwidth, power consumption, stability, input or output matching, reverse isolation, or any combination of these. Such amplifier architectures may be implemented in place of or in addition to the amplifier architectures described herein.

For the plurality of gain modes, different inductances can be provided by the degeneration matrix 230. The degeneration matrix 230 provides tailored impedances in a multi-input amplifier architecture. In one or more gain modes, switches in the multi-input gain stage 212 direct signals to a targeted core of the amplifier architectures 220 which causes the degeneration matrix 230 to couple a particular impedance (e.g., an inductance) to the amplifier 220. In the same gain modes, switches in the multi-input gain stage 212 can direct signals along a different path which results in a different impedance being coupled to the amplifier 220 by the degeneration matrix 230. Providing these impedances with the degeneration matrix 230 can be done to improve linearity of the amplification process, for example, or to provide improved impedance matching and/or improved IIP3. In certain implementations, the path through the multi-input gain stage 212 can change without changing a gain mode and/or can change when changing gain modes.

In some embodiments, the DRx configuration 200 is configured to bypass amplification when operating in a low gain mode and to amplify signals with a particular amplifier architecture 220 when operating in other gain modes. This can advantageously allow the DRx configuration 200 to improve linearity and/or NF in particular gain modes.

In some embodiments, the amplifier 210 is configured to receive a plurality of input signals and to provide a single output signal. In certain embodiments, the amplifier 210 can be configured to receive a plurality of input signals and provide a corresponding plurality of output signals. The filter assembly 272 can be configured to direct signals corresponding to particular frequency bands along designated paths to the amplifier 210. The amplifier 210 can provide different gain modes for the received signals. In certain implementations, the amplifier 210 can provide different gain modes for the received signals. The degeneration matrix 230 can provide different impedances based on the path through the multi-input gain stage 212, the path through the multi-input gain stage 212 (and thus the provided impedance) being based at least in part on the gain mode of the amplifier 210. The amplifier architectures 220 can provide different amplification characteristics so that different gain modes can be amplified using particular amplifier architectures to achieve desired or targeted amplification performance. The particular amplifier architecture that is selected, such as the low NF core 222 or the high linearity core 224, can be based on the gain mode of the amplifier 210. In certain implementations, the amplifier 210 can operate in a bypass configuration such that the signal passes through a bypass path 240 and in an amplification configuration such that the signal passes through an amplification path that includes a selected amplifier architecture, such as low NF core 222 or high linearity core 224. This can advantageously allow the DRx FEM 208 to provide variable gain and/or a plurality of gain modes while reducing the negative impacts on linearity (e.g., IIP3) and/or noise factor (NF) relative to configurations that do not selectively provide amplifier architectures for particular gain modes. The amplifier 210 can include any suitable amplifier circuit configured to provide a desired or targeted amplification. In some embodiments, the amplifier 210 includes a low-noise amplifier (LNA) circuit configured to amplify signals from a plurality of frequency bands (e.g., cellular frequency bands and/or WLAN frequency bands) received at a plurality of inputs, or a multi-input LNA. However, it is to be understood that the embodiments described herein are not to be limited to implementations that utilize low-noise amplifiers but include implementations that use any of a variety of amplifiers.

The amplifier 210 can be configured to amplify signals based at least in part on a plurality of gain modes. For example, the amplifier 210 can be configured to provide a first amplification or gain for a first gain mode, a second amplification or gain for a second gain mode, and so on. The amplifier 210 can be controlled by the controller 102 to control the gain provided at the amplifier 210. For example, the controller 102 can provide a signal indicative of a desired or targeted gain to the amplifier 210 and the amplifier 210 can provide the targeted gain. The controller 102 may receive an indication of the targeted gain from another component in a wireless device, for example, and control the amplifier 210 based at least in part on that indication. Similarly, the amplifier architectures 220 can be activated based at least in part on a gain mode and/or targeted gain of the amplifier 210. Likewise, the degeneration matrix 230 can provide a tailored impedance based at least in part on the path through the multi-input gain stage 212 which can be determined by the gain mode and/or targeted gain of the amplifier 210.

The controller 102 can be configured to control the DRx FEM 208 to selectively provide tailored gain performance due at least in part to a tailored impedance provided by the degeneration matrix 230. For example, the controller 102 and the DRx FEM 208 can control the amplifier architectures 220 to direct signals to a targeted amplifier core (e.g., low NF core 222 or high linearity core 224) based at least in part on a gain mode. As another example, the controller 102 and the DRx FEM 208 can control the amplifier 210 to provide a bypass path 240 based at least in part on a gain mode. As another example, the controller 102 and the DRx FEM 208 can use the amplifier 210 to provide a plurality of gain modes.

Example Architectures of Variable Gain Amplifiers

Front-end modules generally include amplifiers such as low-noise amplifiers (LNAs) to amplify received signals. In wireless devices that provide a variety of gain modes, it may be advantageous to selectively direct signals through amplifier cores that provide targeted performance characteristics, such as low NF and/or high linearity, to improve or optimize amplifier performance. Additionally, in wireless devices that provide a variety of gain modes, it may be advantageous to selectively provide tailored impedances at a gain stage to improve performance. Similarly, for at least one gain mode, it may be advantageous to bypass a gain stage to improve performance (e.g., linearity).

Accordingly, provided herein are variable gain amplifiers that selectively direct signals to particular amplifier architectures depending at least in part on a gain mode of the variable gain amplifier. The selected amplifier architecture determines a tailored impedance provided by a degeneration matrix, wherein the degeneration matrix does not include any switches. This advantageously reduces or eliminates performance penalties in one or more gain modes. Similarly, this advantageously increases or optimizes performance characteristics in one or more gain modes. Furthermore, the amplifier architectures can be configured to improve NF and/or linearity of the amplification process in targeted gain modes. Moreover, this reduces the size and complexity of the degeneration matrix, thereby reducing the size and complexity of the amplifier. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality.

FIG. 3A illustrates an example variable gain amplifier configuration 310 a that includes a switchable reference bias 315, a gain mode selector 321, a bypass block 340, and a plurality of amplifier architectures 320 configured to receive input signals and to selectively amplify the received signals with a selected amplifier architecture 320 or to provide a bypass path through the bypass block 340. The gain mode selector 312 is configured to direct signals to the amplifier architectures 320 and to a degeneration matrix 330 that is configured to provide tailored impedances based at least in part on a gain mode of the variable gain amplifier configuration 310 a and/or a path through the gain mode selector 312. The gain mode selector 312 is configured to direct signals to a selected amplifier architecture 320 (e.g., a high gain stage 322 or a low gain stage 324) or to the bypass block 340 based at least in part on a gain mode of the amplifier configuration 310 a. The gain mode selector 312 includes elements that can switch the signal path from the input to the targeted destination (e.g., a selected amplifier architecture 322 or 324 or the bypass block 340). The switched signal path determines the impedance provided by the degeneration matrix 330.

The amplifier architectures 320 include a high gain stage 322 and a low gain stage 324. Each of the high gain stage 322 and the low gain stage 324 can be configured to enhance or emphasize desired performance characteristics, where one or more of the enhanced characteristics can be shared between the gain stages 322, 324 or they can be configured to enhance different characteristics. In some implementations, enhancement of certain performance characteristics may degrade other performance characteristics. However, this may be beneficial where, in a particular gain mode, the enhanced characteristics positively affect amplifier performance more than the degraded characteristics negatively affect amplifier performance. For example, when operating in one or more high gain modes, the gain mode selector 312 can direct signals received from the input to the high gain stage 322. The high gain stage 322 can be configured to reduce NF relative to the low gain stage 324. In a high gain mode, smaller signals are typically received and may be more susceptible to degradation due to noise. Hence, it may be beneficial to tailor the amplifier so that it reduces the NF during amplification. Similarly, when operating in one or more low gain modes, the gain mode selector 312 can direct signals received from the input to the low gain stage 324. The low gain stage 324 can be configured to enhance or boost linearity relative to the high gain stage 322. In a low gain mode, signals are typically larger and less susceptible to noise. Hence, it may be more advantageous to tailor the amplifier so that it enhances linearity than to reduce noise. Accordingly, providing different amplifier architectures for different gain modes allows signals to be directed to advantageous amplifier architectures to achieve desired or targeted performance characteristics.

The switchable reference bias 315 can be configured to provide reference bias voltages to the amplifier architectures 320. The reference bias voltages can be configured to be tailored for a particular gain stage. For example, in one or more high gain modes, the switchable reference bias 315 can provide a first reference bias voltage to the high gain stage 322, and in one or more low gain modes, the switchable reference bias 315 can provide a second reference bias voltage to the low gain stage 324. In this way, the amplifier configuration 310 a can be configured to achieve desired or targeted bias current matching.

The variable gain amplifier configuration 310 a can be further configured to achieve targeted performance characteristics (e.g., relatively high linearity, impedance matching, etc.) through the use of the degeneration matrix 330. The degeneration matrix 330 does not include switches, thereby simplifying and reducing a size of this element of the amplifier configuration 310 a. The impedances provided by the degeneration matrix 330, then, are determined by the path through the gain mode selector 312, which does include switches.

In certain implementations, the bypass block 340 includes a shunt switch that can provide high input to output isolation relative to configurations without such a switch. The variable gain amplifier configuration 310 a can be configured to provide a low-loss direct bypass mode by directing signals from the input through the bypass block 340 and not through the amplifier architectures 320. The low-loss direct bypass mode can be implemented in a low gain mode, for example.

The degeneration matrix 330 is configured to provide impedance to the selected amplifier architecture 320. This can improve performance by providing power and/or noise matching with prior stages in the processing chain. The degeneration matrix 330 can be configured to improve performance (e.g., linearity and/or NF) of the amplifier architectures 320 by providing a feedback mechanism. In some embodiments, the degeneration matrix 330 is configured to provide a first impedance for a first gain mode and a second impedance for a second gain mode, the impedances determined by the path through the gain mode selector 312. The tailored impedances provided by the degeneration matrix 330 can also be configured to improve linearity of the selected amplifier architecture 320. The variable gain amplifier configuration 310 a can be configured to bypass the degeneration matrix 330 in a bypass mode. This can improve linearity performance by reducing or minimizing leakage current passing through the selected amplifier architecture 320.

The bypass block 340 is configured to receive signals from the gain mode selector 312 and to provide a path to the output that does not pass through the amplifier architectures 320 or the degeneration matrix 330. The bypass block 340 can include components that serve to isolate the input and output in one or more of the gain modes provided by the variable gain amplifier configuration 310 a.

The bypass selection switch 350 is configured to selectively provide a path from the input through the bypass block 340 to the output or a path from the input through a selected amplifier architecture 320 to the output. The bypass selection switch 350 can include one or more switching elements to isolate and/or to select the desired path based at least in part on a gain mode of the variable gain amplifier configuration 310 a.

In certain embodiments, the variable gain amplifier configuration 310 a can be configured to provide a plurality of gain modes, e.g., gain modes G0, G1, . . . , GN with G0 being the highest gain and GN being a bypass mode. When operating in gain mode GN, the variable gain amplifier configuration 310 a can be configured to direct signals from the input to the bypass block 340. When operating in gain modes G0 to GN−1, the variable gain amplifier configuration 310 a can be configured to direct signals through a selected gain stage 322, 324 and to activate the degeneration matrix 330. The degeneration matrix 330 can be configured to provide different impedance levels for individual gain modes or for groups of gain modes. Even in these gain modes, the bypass block 340 may be at least partially activated by activating a shunt switch in the bypass block 340 to provide isolation between the inputs and the output.

The variable gain amplifier configuration 310 a can be configured to activate the high gain stage 322 for one or more of the gain modes G0 to GN−2 and to activate the low gain stage 324 for one or more of the gain modes G1 to GN−1. In certain implementations, signals are directed to the high gain stage 322 in gain mode G0 and signals are directed to the low gain stage 324 in gain mode GN−1. For gain modes G1 to GN−2, signals may be directed to either the high gain stage 322 or to the low gain stage 324. In some embodiments, the amplifier configuration 310 a can be dynamically configured to direct signals to either the high gain stage 322 or the low gain stage 324 regardless of the gain mode. In some embodiments, the amplifier configuration 310 a can operate in a particular gain mode and can dynamically direct signals to the high gain stage 322 during a first time period and to the low gain stage 324 during a second time period.

The variable gain signal amplifier configuration 310 a can be configured to achieve relatively low noise and high linearity (e.g., higher IIP3) relative to amplifiers with a single amplifier architecture or core. Similarly, the variable gain signal amplifier configuration 310 a can achieve superior performance characteristics relative to amplifiers without multiple amplifier architectures 320, bypass block 340, and/or degeneration matrix 330. The variable gain signal amplifier configuration 310 a can be configured to amplify radio frequency (RF) signals such as cellular signals, WLAN signals, BLUETOOTH® signals, GPS signals, and the like. The variable gain signal amplifier configuration 310 a can be configured to provide broadband capabilities by receiving signals over a plurality of frequency bands at the multiple inputs and processing these signals. The variable gain signal amplifier configuration 310 a can be configured to be controlled by a control circuit assembly, such as a controller (e.g., the controller 102 described herein with reference to FIGS. 1 and 2). The control circuit assembly can intelligently and selectively switch paths between amplifier architectures 320 and a bypass path and can selectively provide impedances with the degeneration matrix 330 by controlling the path through the gain mode selector 312.

The variable gain amplifier configuration 310 a includes multiple inputs, thereby providing a multi-input multi-gain amplifier with switchable active cores and a degeneration matrix 230 that does not include switches. In certain implementations, the amplifier configuration 310 a is configured to receive multiple signals at distinct input ports, each distinct input port configured to receive signals at one or more particular cellular frequency bands. For example, a signal in a first band can be received at a first input port, a signal in a second band can be received at a second input port, and a signal in a third band can be received at a third input port. The variable gain signal amplifier configuration 310 a can be configured to independently process signals at the respective inputs.

It is to be understood that although three inputs are illustrated, the variable gain amplifier configuration 310 a can include any suitable number of inputs. For example, and without limitation, the variable gain amplifier configuration 310 a can include at least 1 input, at least 2 inputs, at least 4 inputs, at least 8 inputs, at least 16 inputs, at least 32 inputs, at least 64 inputs, or at least any number of inputs in the described ranges. As another example and without limitation, the variable gain amplifier configuration 310 a can include less than or equal to 64 inputs, less than or equal to 32 inputs, less than or equal to 16 inputs, less than or equal to 8, less than or equal to 4 inputs, less than or equal to 2 inputs, or less than or equal to any number of inputs in the described ranges.

FIG. 3B illustrates another example variable gain amplifier configuration 310 b that includes the same components as the variable gain amplifier configuration 310 a of FIG. 3A, with additional components. For example, the variable gain amplifier configuration 310 b includes matching networks 318 and 345. The output matching network 318 is configured to provide impedance matching for an output load 316 and the amplifier comprising the amplifier architectures 320 and a cascode buffer 314. The bypass matching network 345 similarly provides impedance matching for the bypass block 340. For the matching networks 318 and 345, any suitable combination of inductors and capacitors can be used to provide the targeted impedances.

The variable gain amplifier configuration 310 b also includes the output load 316 and cascode buffer 314 as part of the amplification chain. The cascode buffer 314 can be configured to act as a current buffer. The cascode buffer 314 is configured to provide isolation between the amplifier architectures 320 and the output. The cascode buffer 314 can also be configured to improve the gain of the active cores 320 of the variable gain amplifier configuration 310 b. The output load 316 is configured to provide a load to current to generate an output voltage swing. The output load 316 can be configured to be tuned or tunable for each band received at the inputs. The output load 316 can be configured to improve return loss and/or increase bandwidth by tailoring the resistance of the output load 316. The current through the output load 316 can be used to set the gain mode of the variable gain amplifier configuration 310 b. For example, a lower current flowing through the output load 316 can be configured to correspond to a lower gain of the variable gain amplifier configuration 310 b.

FIG. 4 illustrates an amplifier 410 that includes an input stage 412 with individual input paths 412 a-c. Each input path 412 a-c includes a corresponding gain stage 411 a-c and a path switch 413 a-c. The amplifier 410 includes a degeneration matrix 430 coupled to the individual paths 412 a-c of the input stage 412. The amplifier 410 also includes a post gain stage 419 that includes circuitry to complete amplification of signals received at the input. The post gain stage 419 can include any suitable circuitry to complete amplification, such as the circuitry described herein with respect to FIGS. 6A and 7.

Signals received at the input are directed along an input path 412 a-412 c by switching on and off the corresponding path switch 413 a-c. This opens a path through the input stage 412 for signals and creates a corresponding entry path 431 a-c into the degeneration matrix 430. The degeneration matrix 430 is configured to provide a tailored impedance (e.g., an inductance) based on the entry path 431 a-c into the degeneration matrix 430. For example, a signal is directed through the first input path 412 a by turning path switch 413 a on and turning off the remaining path switches 413 b, 413 c. The signal is amplified by Gain Stage A 411 a in conjunction with the post gain stage 419, the enabled signal path having a first tailored impedance provided by the degeneration matrix 430 resulting from the entry path 431 a into the degeneration matrix 430. As another example, a signal is directed through the second input path 412 b by turning path switch 413 b on and turning off the remaining path switches 413 a, 413 c. The signal is amplified by Gain Stage B 411 b in conjunction with the post gain stage 419, the enabled signal path having a second tailored impedance provided by the degeneration matrix 430 resulting from the entry path 431 b into the degeneration matrix 430. As another example, a signal is directed through the third input path 412 c by turning path switch 413 c on and turning off the remaining path switches 413 b, 413 c. The signal is amplified by Gain Stage C 411 c in conjunction with the post gain stage 419, the enabled signal path having a third tailored impedance provided by the degeneration matrix 430 resulting from the entry path 431 c into the degeneration matrix 430.

FIG. 5 illustrates a variable-gain signal amplifier 510 that includes a plurality of active cores 522, 524 in a variable-gain stage 520 configured to receive an input signal and to generate an amplified output signal. The amplifier 510 can direct signals to the first active core 522 or to the second active core using a gain mode selector 512, represented as a switch. It should be understood, however, that any combination of electronic elements can be used as the gain mode selector 512 to selectively direct signals to a particular active core. The first active core 522 can be configured to amplify signals while providing enhanced performance characteristics, such as low NF. The first active core 522 can be used in one or more gain modes of the amplifier 510. The second active core 524 can be configured to amplify signals while providing different or overlapping enhanced performance characteristics relative to the first active core 522, such as high linearity.

The active cores 522, 524 can be operated independently of one another. The active cores 522, 524 advantageously allow individual cores to be tailored or optimized for one or more gain modes to improve overall performance of the amplifier 510 across gain modes. Such amplifiers 510 with independent active cores 522, 524 can advantageously allow for easy mapping of particular gain modes to one of the active cores. If it is desirable to achieve different performance characteristics for a particular gain mode, it is not necessary to redesign the amplifier 510 because an individual core can be modified without affecting all gain modes (e.g., gain modes mapped to other active cores). This allows for targeted tuning for particular gain modes. This also allows for dynamic and independent assignment of gain modes to active cores. This also allows particular active cores to be tailored or optimized to satisfy particular performance requirements. For example, in a high gain mode, reducing NF may be of particular interest, so an active core can be designed to reduce NF while other performance characteristics may be degraded. Similarly, in medium or low gain modes, linearity may be of particular interest, so an active core can be designed to enhance linearity while other performance characteristics may be degraded or gain may be decreased. As another example, the active core configured for use in medium or low gain modes can be a different size from an active core configured for use in a high gain mode. Accordingly, different active cores can be of different sizes, types, etc.

In some embodiments, the amplifier 510 can include 3 or more active cores, 4 or more active cores, or 5 or more active cores. In various embodiments, the amplifier 510 can include less than or equal to 10 active cores, less than or equal to 7 active cores, or less than or equal to 5 active cores. In a first gain mode, the amplifier 510 can direct signals through an amplification path that includes the first active core 522. In a second gain mode, the amplifier 510 can direct signals through an amplification path that includes the second active core 524. In some embodiments, the amplifier 510 can direct signals to the first active core 522 for a plurality of gain modes. In certain embodiments, the amplifier 510 can direct signals to the second active core 524 for a plurality of gain modes. In various embodiments, the first active core 522 provides higher gain than the second active core 524. In certain embodiments, the second active core 524 provides lower gain and higher linearity than the first active core 522.

The amplifier includes a degeneration block 530 that provides tailored impedances based on the amplification path selected by the gain mode selector 512. The degeneration block 530 does not include any switches. The amplification path determines an entry point into the degeneration block 530 which in turn determines the tailored impedance provided to the amplification path.

FIGS. 6A and 6B illustrate an example variable gain amplifier configuration 610 that is configured similarly to the variable gain amplifier 310 b described herein with reference to FIG. 3B. The variable gain amplifier 610 includes example electrical components to demonstrate an example implementation of the amplifier 610. It is to be understood, however, that this is merely an illustrative example implementation and the scope of the disclosure extends to additional implementations encompassing similar architectures.

The variable gain amplifier configuration 610 includes a first active core 622, a second active core 624, a bypass block 640, and a degeneration matrix 630. Signals are received at inputs A and B and, depending on the gain mode, directed through the first active core 622, the second active core 624, or the bypass block 640 to the output. Depending on the active core used to amplify the signals, the degeneration matrix 630 provides a tailored impedance. The degeneration matrix 630 does not include any switches. Rather, the inductance provided by the degeneration matrix 630 is determined by the active core used to amplify the signals. For example, signals amplified by the first active core 622 are coupled to the degeneration matrix 630 at point E and see an inductance provided by the inductor L2. As another example, signals amplified by the second active core 624 are coupled to the degeneration matrix 630 and see an inductance provided by a combination of the inductors L1 and L2.

In some embodiments, the first active core 622 is configured to amplify signals in a high gain mode or in a plurality of high gain modes, the first active core 622 configured to reduce NF relative to the second active core. In some embodiments, the second active core 624 is configured to amplify signals in a low gain mode or in a plurality of low gain modes, the second active core 624 configured to enhance linearity or improve IIP3 relative to the first active core 622. The bypass block 640 is configured to provide signals a bypass path in a lowest gain mode. In some embodiments, the first active core 622 can be referred to as a high gain core or a low NF core. In some embodiments, the second active core 624 can be referred to as a linearity boost core, a medium gain core, or a low gain core.

The first active core 622 includes a multi-input gain stage 612 configured to receive inputs A and B and to selectively amplify the received signals with corresponding transistors Q1 and Q2 in conjunction with corresponding transistors Q3 and Q4 and a cascode buffer 614 a with the transistor Q5.

The multi-input gain stage 612 provides a voltage to current gain stage comprising the transistors Q1 and Q2. Further, the multi-input gain stage 612 is configured to amplify respective input signals in conjunction with transistors Q3 and Q4 and the cascode buffer 614 a that acts as a current buffer to lower input impedance and to increase output impedance.

The first active core 622 includes isolation switch 613, having switch S5, configured to isolate input to the first active core 622 from the second active core 624 when the first active core 622 is active and to isolate input to the bypass block 640 from the second active core 624 when operating in a bypass mode. In other words, switch S5 in the isolation switch 613 is open when the second active core 624 is active and closed during other operating modes (e.g., other gain modes or bypass mode). The amplifier configuration 610 also includes a similar bypass isolation switch 644, having switch S6, in the bypass block 640 to isolate input to the first active core 622 and the second active core 624 from the bypass block 640. In other words, switch S6 in the bypass isolation switch 644 is open when operating in bypass mode and closed during other operating modes (e.g., other gain modes).

The first active core 622 includes switches to selectively direct signals to the second active core 624 rather than through the first active core 622. It is to be understood that although the switches are shown as part of the first active core, these switching elements can be implemented in any part of the amplifier configuration 610. Switches S1 and S4 respectively direct input signals from inputs A and B to the bypass block 640. Switches S2 and S3 respectively direct input signals from inputs A and B to the second active core 624 through the point C. The switches S1-S4 can be implemented using any suitable switching components, such as switches, transistors, or the like. The switches S1-S4 can be operated based at least in part on the gain mode of the amplifier configuration 610. For example, in a high gain mode, the switches S1-S4 can be open to direct signals from inputs A or B through the first active core. In one or more other gain modes, the switches S2 or S3 can be closed (with the remaining switches open) to direct signals through the second active core 624. In a bypass mode or in a lowest gain mode, the switches S1 or S4 can be closed (with the remaining switches open) to direct signals along a bypass path through the bypass block 640.

Similar to the first active core 622, the second active core 624 has an amplification chain that includes a transistor Q6 and a cascode buffer 614 b with the transistor Q7. The gate voltages can be different for different cascode buffers 614 a, 614 b in the different active cores 622, 624. Linearity depends at least in part on how the cascode buffers 614 a, 614 b are biased. This provides an additional method of tuning performance of the active cores 622, 624, e.g., to enhance linearity in the second active core 624 relative to the first active core 622.

The second active core 624 includes a feedback cap 617 coupled to the point C through the transistor Q7, or the input to the second active core 624 from input A or input B. The variable capacitor can be tuned to improve IIP3 linearity and/or to match input impedance. The feedback cap 617 is configured to provide a way to control linearity of the amplification process and to provide a targeted input impedance. In some embodiments, similar feedback caps can be included in the first active core between the output and inputs A and B, respectively, to provide a way to control linearity of the amplification process and/or to provide a targeted input impedance. The feedback cap 617 is optional in the amplifier configuration 610.

The second active core 624 includes the degeneration matrix 630 that is configured to provide tailored impedances based at least in part on an amplification path (e.g., the active core used to amplify signals) through the variable gain amplifier configuration 810. The degeneration matrix 630 is also coupled to the amplification path of the first active core 622 at point E. In this way, the first active core 622 and the second active core 624 share the degeneration matrix 630 with different entry points into the degeneration matrix 630 resulting in different inductances provided by the degeneration matrix 630.

In certain implementations, the multi-input gain stage 612 is configured to receive multiple signals at distinct input ports, each distinct input port configured to receive signals at one or more particular cellular frequency bands. For example, input A receives a signal in a first band and input B receives a signal in a second band.

The degeneration matrix 630 is configured to provide impedance to the gain stage of the multi-input gain stage 612 of the first active core 622 or the transistor Q6 of the second active core 624. This can improve performance by providing power and/or noise matching with prior stages in the processing chain. The degeneration matrix 630 can be configured to improve linearity of the gain stage (e.g., transistors Q1, Q2, or Q6) by providing a feedback mechanism. The degeneration matrix 630 can be configured to provide a first impedance L2 for a first gain mode through the first active core 622 and a second impedance provided by L1 and L2 for a second gain mode through the second active core 624. The impedances provided by the degeneration matrix 630 can also be configured to improve linearity of the gain stage. In a bypass mode, the degeneration matrix 630 can be decoupled from the signal path using switches S2 and S3. The variable gain amplifier configuration 610 can be configured to bypass the first active core 622 and the second active core 624 in a bypass mode. This can improve linearity performance by reducing or minimizing leakage current passing through the respective active cores 622, 624. In certain implementations, the degeneration matrix 630 can be configured to provide a lower inductance for higher gain modes.

The degeneration matrix 630 can be configured to provide tailored inductances to increase performance of the variable gain amplifier 610 relative to an amplifier with fixed inductance. Performance can be increased by increasing linearity and/or by reducing noise introduced during amplification, for example.

The bypass block 640 is configured to receive signals from the multiple inputs and to provide a path to the output that does not pass through the first active core 622 or the second active core 624. The bypass block 640 is configured to provide a path to the output through tunable matching network 645, similar to the matching network 345 described herein with reference to FIG. 3B. The bypass block 640 can be configured to provide two paths to the output, a direct path and an output tank path, activated by closing switch S7. The output tank path is directed to a path that is coupled to an output load 816 at point D, the output load similar to the output load 316 described herein with reference to FIG. 3B. The bypass block 640 also includes a bypass isolation switch 644, or shunt switch, that selectively couples the bypass block 640 to a reference potential node to aid in isolating the inputs from the output. The bypass matching network 645 can provide additional impedance matching flexibility.

The variable gain amplifier configuration 610 can be configured to achieve relatively high linearity through the use of the degeneration matrix 630. The variable gain amplifier configuration 610 can be configured to provide a low-loss direct bypass mode by directing signals from the inputs through the bypass block 640. The low-loss direct bypass mode can be implemented in a low gain mode, for example.

The amplifier configuration 610 includes a bypass selection switch 650 that is configured to selectively provide a path from input A or input B through the bypass block 640 to the output or a path from input A or input B through one of the active cores 622, 624 to the output. The bypass selection switch 650 includes switches S8 and S9 that respectively control connection of a bypass path to the output and an amplification path to the output. The bypass selection switch 650 can be controlled based at least in part on a gain mode of the variable gain amplifier 610.

The matching networks 618 and 645 can include any suitable combination of inductors and capacitors that can be used to provide targeted impedances. The output matching network 618 is configured to provide impedance matching for an output load 616 and active cores 622, 624. The bypass matching network 645 similarly provides impedance matching for the bypass block 640.

The variable gain amplifier 610 includes the output load 616 and cascode buffers 614 a, 614 b as part of the amplification path. The cascode buffers 614 a, 614 b includes respective transistors Q5 and Q7 that are configured to act as current buffers. The cascode buffers 614 a, 614 b are configured to provide isolation between the gain stages of the respective active cores 622, 624 and the output. The cascode buffers 614 a, 614 b can also be configured to provide a targeted gain for the respective active cores 622, 624. The output load 616 is configured to provide a load to current to generate an output voltage swing. The output load 616 can be configured to be tuned or tunable for each band received at the inputs. For example, the output load 616 includes a variable capacitor C1 that can be tuned for particular cellular frequency bands. The output load 616 can also be configured to improve return loss and/or increase bandwidth by tailoring the resistance R1 of the output load 616.

Each of the transistors Q1, Q2, and Q6 of the active cores 622, 624 include a leakage control switch 611 a-c. The leakage control switches 611 a-c are configured to control leakage to improve linearity performance in the bypass mode. The leakage control switches 611 a-c can be turned on in the bypass mode.

FIG. 6B illustrates a switchable reference bias circuit 615 used in conjunction with the amplifier configuration 610 of FIG. 6A. The switchable reference bias circuit 615 is coupled to the amplifier configuration 610 of FIG. 6A at points A, B, and F. The switchable reference bias circuit 615 includes a power supply voltage, VDD, and a current source, IDD. The current is selectively directed through transistors Q1-Q3 through the use of switches S1-S6. This can be used to provide targeted current matching for the active cores 622, 624. For example, switches S2 and S3 can be closed and switches S1 and S4 can be opened when operating in a gain mode that uses the first active core 622 to amplify signals from input A. Similarly, switches S1 and S4 can be closed and switches S2 and S3 can be opened when operating in a gain mode that uses the first active core 622 to amplify signals from input B. Likewise, switch S6 can be closed and switch S5 can be opened when operating in a gain mode that uses the second active core 624 to amplify signals either from input A or input B. In some embodiments, when amplifying signals from input A or input B with the first active core 622, switches S5 and S6 are opened to deactivate transistor Q3 in the switchable reference bias circuit 615. Similarly, when amplifying signals with the second active core 624, switches S1-S4 are opened to deactivate transistors Q1 and Q2. This can be extended to more than two inputs (e.g., inputs in addition to input A and input B).

The switchable reference bias circuit 615 includes a resistor between the point A and the switch S3, a resistor between the point B and the switch S4, and a resistor between the point F and the switch S6. These resistors are configured to isolate the switchable reference bias circuit 615 from the active amplification cores. The resistors can be configured to provide a relatively high RF impedance to the switchable reference bias circuit 615 and/or to prevent or reduce noise from passing from the switchable reference bias circuit 615 to the active amplification core 622, 624.

It is to be understood that although FIGS. 6A and 6B illustrate an amplifier configuration 610 having two inputs (inputs A and B), the amplifier configuration 610 can be configured to receive more than 2 inputs, such as 3 or more inputs, 4 or more inputs, 5 or more inputs, etc.

FIG. 7 illustrates another example amplifier configuration 710 that is similar to the amplifier configuration 610 described herein with reference to FIGS. 6A and 6B. The difference between the amplifier configuration 710 and the amplifier configuration 610, is that the amplifier configuration 710 removes the cascode buffer 614 b and instead connects the second active core 624 to the cascode buffer 614 a at the point G. In addition, the optional feedback cap 617 has been removed to illustrate the circuit without that component.

FIGS. 8A-8F illustrate examples of operating modes of the variable gain signal amplifier configuration 610 of FIG. 6A. FIGS. 8A and 8B illustrate operation in one or more high gain modes, which may also be referred to as low NF modes, for amplifying signals from input A and input B, respectively. In these high gain modes, the first active core 622 is activated, the second active core 624 is deactivated, and the bypass block 640 is deactivated, except for the bypass isolation switch 644 (which is closed). In each of these high gain modes, the degeneration matrix 630 provides an inductance to the amplification path through the inductor L2. In FIG. 8A, signals received at the input A are directed through the multi-input gain stage 612 comprising transistor Q1, through transistor Q3, and through the cascode buffer 614 a to the output through the output matching network 618 and the bypass selection switch 650. Similarly, in FIG. 8B, signals received at the input B are directed through the multi-input gain stage 612 comprising transistor Q2, through transistor Q4, and through the cascode buffer 614 a to the output through the output matching network 618 and the bypass selection switch 650. The bypass selection switch 650 closes switch S9 and opens switch S8 in these high gain modes. For signals from both input A and input B, the amplifier configuration 610 provides inductive degeneration to the gain stage through inductor L2. Switches S1-S4 are open so signals do not propagate to the second active core 624 or the bypass block 640. Furthermore, isolation switch 613 is closed to further isolate the inputs from the second active core 624.

FIGS. 8C and 8D illustrate operation in one or more medium gain modes for amplifying signals from input A and input B. These modes may also be referred to as low gain or high linearity modes. In these medium gain modes, the first active core 622 is deactivated, the second active core 624 is activated, and the bypass block 640 is deactivated, except for the bypass isolation switch 644 (which is closed). In these medium gain modes, the degeneration matrix 630 provides an inductance to the amplification path using the inductors L1 and L2. In FIG. 8C, signals received at input A are directed to the point C through closed switch S2 (with switch S3 open). Similarly, in FIG. 8D, signals received at input B are directed to the point C through closed switch S3 (with switch S2 open). For signals received from input A or input B, the signals then pass through transistor Q7 and gain stage transistor Q6 and cascode buffer 614 b to the output through the output matching network 618 and the bypass selection switch 650. The bypass selection switch 650 closes switch S9 and opens switch S8 in these medium gain modes. The degeneration matrix 630 provides a tailored inductance to the second active core 624 using the combination of inductors L1, L2. This allows the second active core 624 to increase impedance for lower gain modes, or, to decrease impedance for higher gain modes. Switches S1 and S4 are open so signals do not propagate to the bypass block 640. Furthermore, isolation switch 613 is open to allow signals to propagate to the second active core 624. Optionally, the feedback cap 617 is activated to provide a feedback loop to the second active core 624.

FIG. 8E illustrates operation in a low gain mode or a passive bypass mode for signals received from input A or input B. In the bypass mode, the bypass block 640 is activated and the active cores 622, 624 are deactivated, except isolation switch 613 (which is closed). Signals received at input A are directed through the bypass block 640 by closing switch S1 and through the bypass matching network 645 and to the output through the bypass selection switch 650 by opening switch S9 and closing switch S8. Signals received at input B are directed through the bypass block 640 by closing switch S4 and through the bypass matching network 645 and to the output through the bypass selection switch 650. In bypass mode for input A, switch S1 is closed with switches S2, S3, and S4 open. In bypass mode for input B, switch S4 is closed with switches S1, S2, and S3 open. The bypass isolation switch 644 is deactivated in the bypass mode.

FIG. 8F illustrates operation in the low gain mode or the passive bypass mode for signals received from input A or input B. This bypass path is coupled to the tunable output load 616 at point D, activated by closing switches S7 and S9 and opening switch S8. It should be noted that signals from input A can be routed to the output through the path that includes point D, and that signals from input B can be routed to the output through the path that does not include point D.

Examples of Products and Architectures

FIG. 9 illustrates that in some embodiments, some or all of the amplifier configurations, including some or all of the amplifier configurations having the combinations of features described herein (e.g., FIGS. 1-8F), can be implemented, wholly or partially, in a module. Such a module can be, for example, a front-end module (FEM). Such a module can be, for example, a diversity receiver (DRx) FEM. Such a module can be, for example, a multi-input, multi-output (MiMo) module.

In the example of FIG. 9, a module 906 can include a packaging substrate 901, and a number of components can be mounted on such a packaging substrate 901. For example, a controller 902 (which may include a front-end power management integrated circuit [FE-PIMC]), a combination assembly 907, a variable gain amplifier assembly 910 that includes switchable active cores 920 and a degeneration matrix 930 having one or more features as described herein, and a filter bank 909 (which may include one or more bandpass filters) can be mounted and/or implemented on and/or within the packaging substrate 901. Other components, such as a number of SMT devices 905, can also be mounted on the packaging substrate 901. Although all of the various components are depicted as being laid out on the packaging substrate 901, it will be understood that some component(s) can be implemented over other component(s).

In some implementations, a device and/or a circuit having one or more features described herein can be included in an RF electronic device such as a wireless device. Such a device and/or a circuit can be implemented directly in the wireless device, in a modular form as described herein, or in some combination thereof. In some embodiments, such a wireless device can include, for example, a cellular phone, a smart-phone, a hand-held wireless device with or without phone functionality, a wireless tablet, etc.

FIG. 10 depicts an example wireless device 1000 having one or more advantageous features described herein. In the context of one or more modules having one or more features as described herein, such modules can be generally depicted by a dashed box 1006 (which can be implemented as, for example, a front-end module) and a diversity receiver (DRx) module 1008 (which can be implemented as, for example, a front-end module).

Referring to FIG. 10, power amplifiers (PAs) 1082 can receive their respective RF signals from a transceiver 1004 that can be configured and operated to generate RF signals to be amplified and transmitted, and to process received signals. The transceiver 1004 is shown to interact with a baseband sub-system 1005 that is configured to provide conversion between data and/or voice signals suitable for a user and RF signals suitable for the transceiver 1004. The transceiver 1004 can also be in communication with a power management component 1007 that is configured to manage power for the operation of the wireless device 1000. Such power management can also control operations of the baseband sub-system 1005 and the modules 1006 and 1008.

The baseband sub-system 1005 is shown to be connected to a user interface 1001 to facilitate various input and output of voice and/or data provided to and received from the user. The baseband sub-system 1005 can also be connected to a memory 1003 that is configured to store data and/or instructions to facilitate the operation of the wireless device, and/or to provide storage of information for the user.

In the example wireless device 1000, outputs of the PAs 1082 are shown to be matched (via respective match circuits 1084) and routed to their respective duplexers 1086. Such amplified and filtered signals can be routed to a primary antenna 1060 through a switching network 1009 for transmission. In some embodiments, the duplexers 1086 can allow transmit and receive operations to be performed simultaneously using a common antenna (e.g., primary antenna 1060). In FIG. 10, received signals are shown to be routed to a variable gain amplifier assembly 1010 a, which provides the features and benefits of the variable gain amplifiers described herein. The DRx module 1008 includes a similar variable gain amplifier assembly 1010 b as well.

In the example wireless device 1000, signals received at the primary antenna 1060 can be sent to a variable gain amplifier 1010 a in the front-end module 1006. The variable gain amplifier 1010 a can include switchable active cores 1020 and a degeneration matrix 1030 that does not include switches. The variable gain amplifier 1010 a is configured to receive a plurality of signals at inputs 1011 and to output a plurality of processed signals at outputs 1019. The variable gain amplifier 1010 a is configured to amplify signals by directing signals through a particular active core based at least in part on a gain mode. This can be done to improve NF for high gain modes and to improve linearity for signals for medium and/or low gain modes relative to variable gain amplifiers that do not include one or more of the described features. The path through the variable gain amplifier 1010 a is configured to determine the impedance provide by the degeneration matrix 1030, as described herein. In at least one low gain mode, the switchable active cores 1020 can be bypassed.

The wireless device also includes a diversity antenna 1070 and a diversity receiver module 1008 that receives signals from the diversity antenna 1070. The diversity receive module 1008 includes a variable gain amplifier 1010 b, similar to the variable gain amplifier 1010 a in the front-end module 1006. The diversity receiver module 1008 and the variable gain amplifier 1010 b process the received signals and transmit the processed signals to the transceiver 1004. In some embodiments, a diplexer, triplexer, or other multiplexer or filter assembly can be included between the diversity antenna 1070 and the diversity receiver module 1070, as described herein.

One or more features of the present disclosure can be implemented with various cellular frequency bands as described herein. Examples of such bands are listed in Table 1. It will be understood that at least some of the bands can be divided into sub-bands. It will also be understood that one or more features of the present disclosure can be implemented with frequency ranges that do not have designations such as the examples of Table 1. It is to be understood that the term radio frequency (RF) and radio frequency signals refers to signals that include at least the frequencies listed in Table 1.

TABLE 1 Tx Frequency Range Rx Frequency Range Band Mode (MHz) (MHz) B1 FDD 1,920-1,980 2,110-2,170 B2 FDD 1,850-1,910 1,930-1,990 B3 FDD 1,710-1,785 1,805-1,880 B4 FDD 1,710-1,755 2,110-2,155 B5 FDD 824-849 869-894 B6 FDD 830-840 875-885 B7 FDD 2,500-2,570 2,620-2,690 B8 FDD 880-915 925-960 B9 FDD 1,749.9-1,784.9 1,844.9-1,879.9 B10 FDD 1,710-1,770 2,110-2,170 B11 FDD 1,427.9-1,447.9 1,475.9-1,495.9 B12 FDD 699-716 729-746 B13 FDD 777-787 746-756 B14 FDD 788-798 758-768 B15 FDD 1,900-1,920 2,600-2,620 B16 FDD 2,010-2,025 2,585-2,600 B17 FDD 704-716 734-746 B18 FDD 815-830 860-875 B19 FDD 830-845 875-890 B20 FDD 832-862 791-821 B21 FDD 1,447.9-1,462.9 1,495.9-1,510.9 B22 FDD 3,410-3,490 3,510-3,590 B23 FDD 2,000-2,020 2,180-2,200 B24 FDD 1,626.5-1,660.5 1,525-1,559 B25 FDD 1,850-1,915 1,930-1,995 B26 FDD 814-849 859-894 B27 FDD 807-824 852-869 B28 FDD 703-748 758-803 B29 FDD N/A 716-728 B30 FDD 2,305-2,315 2,350-2,360 B31 FDD 452.5-457.5 462.5-467.5 B32 FDD N/A 1,452-1,496 B33 TDD 1,900-1,920 1,900-1,920 B34 TDD 2,010-2,025 2,010-2,025 B35 TDD 1,850-1,910 1,850-1,910 B36 TDD 1,930-1,990 1,930-1,990 B37 TDD 1,910-1,930 1,910-1,930 B38 TDD 2,570-2,620 2,570-2,620 B39 TDD 1,880-1,920 1,880-1,920 B40 TDD 2,300-2,400 2,300-2,400 B41 TDD 2,496-2,690 2,496-2,690 B42 TDD 3,400-3,600 3,400-3,600 B43 TDD 3,600-3,800 3,600-3,800 B44 TDD 703-803 703-803 B45 TDD 1,447-1,467 1,447-1,467 B46 TDD 5,150-5,925 5,150-5,925 B65 FDD 1,920-2,010 2,110-2,200 B66 FDD 1,710-1,780 2,110-2,200 B67 FDD N/A 738-758 B68 FDD 698-728 753-783

Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed in parallel, or may be performed at different times.

The teachings of the invention provided herein can be applied to other systems, not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments.

While some embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure. 

What is claimed is:
 1. A variable-gain signal amplifier configured to provide a plurality of gain modes, the amplifier comprising: an input node configured to receive an input signal; an output node configured to provide an amplified output signal; a first active core configured to receive the input signal and to generate the amplified output signal for the output node; a second active core configured to receive the input signal and to generate the amplified output signal for the output node; a gain mode selector configured to direct the input signal to the first active core in a first gain mode and to direct the input signal to the second active core in a second gain mode different from the first gain mode; and a degeneration matrix configured to provide tailored inductances depending on a signal path determined by the gain mode selector, the degeneration matrix not including any switches.
 2. The amplifier of claim 1 wherein the input signal comprises a radio frequency signal.
 3. The amplifier of claim 1 further comprising a switchable reference bias circuit configured to provide a first reference bias current to the first active core in the first gain mode and a second reference bias current to the second active core in the second gain mode.
 4. The amplifier of claim 1 wherein the gain mode selector is configured to selectively provide a bypass path that bypasses the first active core and the second active core and an amplification path that passes through either the first active core or the second active core.
 5. The amplifier of claim 1 wherein the degeneration matrix is configured to provide a first inductance to the first active core and a second inductance different from the first inductance to the second active core.
 6. The amplifier of claim 1 wherein the tailored impedances are configured to provide improved linearity in the amplified output signal relative to a variable gain stage that is not coupled to the degeneration matrix with the tailored impedances.
 7. The amplifier of claim 1 wherein the degeneration switching block is configured to provide a first tailored impedance for the first gain mode and a second tailored impedance for the second gain mode.
 8. The amplifier of claim 7 wherein the first tailored impedance is greater than the second tailored impedance and the first gain level is less than the second gain level.
 9. The amplifier of claim 1 wherein the first active core is configured to have a lower noise figure than the second active core.
 10. The amplifier of claim 9 wherein the second active core is configured to have a higher linearity than the first active core.
 11. The amplifier of claim 10 wherein the first gain mode is higher than the second gain mode.
 12. The amplifier of claim 1 further comprising a plurality of input nodes.
 13. The amplifier of claim 12 wherein the amplifier is configured to receive a plurality of input signals at the plurality of input nodes, individual received signals having frequencies within different signal frequency bands.
 14. The amplifier of claim 13 wherein the amplifier is configured to amplify signals received at individual input ports independent of amplification of other received signals.
 15. The amplifier of claim 1 further comprising a bypass block coupled to the input node and configured to be activated in a low gain mode to provide a bypass path that does not include the first active core and the second active core.
 16. The amplifier of claim 1 wherein each of the first active core and the second active core include a cascode buffer coupled to an output of a gain stage.
 17. A front-end module comprising: a packaging substrate; a variable gain signal amplifier implemented on the packaging substrate, the variable gain signal amplifier including a first active core configured to receive an input signal and to generate an amplified output signal, a second active core configured to receive the input signal and to generate the amplified output signal, a gain mode selector configured to direct the input signal to the first active core in a first gain mode and to direct the input signal to the second active core in a second gain mode, a degeneration matrix configured to provide tailored inductances depending on a signal path determined by the gain mode selector, the degeneration matrix not including any switches, and a controller implemented to control the variable gain signal amplifier to provide a plurality of gain modes including the first gain mode and the second gain mode.
 18. The module of claim 17 wherein the gain signal amplifier further includes a switchable reference bias circuit configured to provide independent bias currents to the first active core and to the second active core.
 19. The module of claim 17 wherein the first active core is configured to have a lower noise figure than the second active core and the second active core is configured to have a higher linearity than the first active core.
 20. A wireless device comprising: an antenna; a filter assembly coupled to the antenna to receive signals and to direct frequency bands along select paths; and a variable gain signal amplifier including a first active core configured to receive an input signal and to generate an amplified output signal, a second active core configured to receive the input signal and to generate the amplified output signal, a gain mode selector configured to direct the input signal to the first active core in a first gain mode and to direct the input signal to the second active core in a second gain mode, and a degeneration matrix configured to provide tailored inductances depending on a signal path determined by the gain mode selector, the degeneration matrix not including any switches; and a controller implemented to control the variable gain signal amplifier to provide a plurality of gain modes. 